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46 IBM BladeCenter JS23 and JS43 Implementation Guide

Enhanced SMT features

To improve SMT performance for various workloads and provide robust quality of

service, POWER6 provides two features:

򐂰 Dynamic resource balancing

The objective of dynamic resource balancing is to ensure that the two threads

executing on the same processor flow smoothly through the system.

Depending on the situation, the POWER6 processor resource balancing logic

has a different thread throttling mechanism (a thread reached threshold of L2

cache misses and will be throttled to allow other threads to pass the stalled

thread).

򐂰 Adjustable thread priority

Adjustable thread priority lets software determine when one thread should

have a greater (or lesser) share of execution resources. POWER6 supports

eight software-controlled priority levels for each thread.

Single-threaded (ST) operation

Not all applications benefit from SMT. Having threads executing on the same

processor does not increase the performance of applications with execution unit

limited performance or applications that consume all the chip’s memory

bandwidth. For this reason, POWER6 supports the ST execution mode. In this

mode, the POWER6 processor gives all the physical resources to the active

thread. Highly optimized scientific codes are one example where ST operation is

ideal.

3.3 AltiVec (SIMD)

IBM Semiconductor’s advanced Single Instruction, Multiple Data (SIMD)

technology based on the AltiVec instruction set is designed to enable exceptional

general-purpose processing power for high-performance POWER processors.

This leading-edge technology is engineered to support high-bandwidth data

processing and algorithmic-intensive computations, all in a single-chip solution.

With its computing power, AltiVec technology also enables high-performance

POWER processors to address markets and applications in which performance

must be balanced with power consumption, system cost, and peripheral

integration.

The AltiVec technology is a well-known environment for software developers who

want to add efficiency and speed to their applications. A 128-bit vector execution

unit was added to the architecture. This engine operates concurrently with the

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